1. Field of the Invention
The present invention relates to a circuit board and a process of fabricating the same. More particularly, the present invention relates to a circuit board in which a circuit layer includes two regions with different thicknesses and a process of fabricating said circuit board.
2. Description of Related Art
A wire bonding technology is a common chip packaging technology applied to electrically connect a chip to a carrier. Here, the carrier is, for example, a circuit board. Generally, the wire bonding technology includes forming a stud bump in a wire bonding pad region of the carrier with use of a stud bump machine and extending wires upward with a distance. After that, the wires are moved downward to a chip pad region and are stitched. By applying the wire bonding technology, the chip and the carrier can be electrically connected to each other by means of the wires, and thereby signals can be transmitted between the chip and the carrier through the wires.
FIG. 1A is a schematic top view of a normal wire bonding structure of a circuit board according to the pertinent art. FIG. 1B is a cross-sectional view of the circuit board depicted in FIG. 1A along a line I-I. Referring to FIGS. 1A and 1B, a conventional circuit board 10 includes a dielectric layer 12, a circuit layer 14, and a solder mask layer 16. The circuit layer 14 is disposed on the dielectric layer 12 and has a trace region 14a and a wire bonding pad region 14b. The solder mask layer 16 is disposed on the circuit layer 14, and the circuit layer 14 covers the trace region 14a. 
When a wire bonding process is implemented, a stud bump b is formed on the wire bonding pad region 14b and is electrically connected to the circuit layer 14 through the wire bonding pad region 14b. The stud bump b depicted in FIGS. 1A and 1B are normally located at the center of the wire bonding pad region 14b, and therefore stresses and pulling forces applied to the wire bonding pad region 14b can be evenly distributed onto the circuit board 10 during implementation of the wire bonding process.
FIG. 2A is a schematic top view of an abnormal wire bonding structure of a circuit board according to the pertinent art. FIG. 2B is a cross-sectional view of the circuit board depicted in FIG. 2A along a line II-II. Referring to FIGS. 2A and 2B, a circuit board 20 depicted in FIG. 2A is similar to the circuit board 10 depicted in FIG. 1A, while a difference therebetween lies in that a stud bump b is located at an edge of a wire bonding pad region 24b rather than at the center thereof due to errors occurring in the wire bonding process.
Specifically, according to the pertinent art, a thickness of a trace region 24a and a thickness of the wire bonding pad region 24b are the same, approximately 20 micro meters. Hence, when the stud bump b is located at the edge of the wire bonding pad region 24b, the stud bump b is less supported by a dielectric layer 22 in comparison with the stud bump b of FIGS. 1A and 1B. That is to say, stresses and pulling forces applied to the wire bonding pad region 24b are not able to be evenly distributed onto the circuit board 20, thereby generating a non-stick effect.
Nonetheless, in order to resolve the issue regarding the non-stick effect generated between the stud bump b and the wire bonding pad region 24b, a thickness of the trace region 24a and a thickness of the wire bonding pad region 24b are reduced from 20 micro meters to 10 micro meters. As such, the trace region 24a with the reduced thickness is less stress-resistant, and cracks would then be formed.